Forum Discussion
prateekmohan
New Contributor
New ContributorPCIe Avalon-MM to DDR Write and Read
Hello,
I am looking at methods to write/read from DDR from my host system through the PCIe Hard IP block.
I have looked at some examples for Qsys projects using the PCIe Hard IP block and I under...
Deshi_Intel
Regular Contributor
Regular ContributorHI,
The AN708 was older ref design doc that pointed to old outdated Altera ref design link that doesn't exist in Intel system anymore.
If you are looking for A10 PCIe example design, you can generate the example design directly from PCIe IP. Check out below link
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-a10-pcie-avmm.pdf
- This example design is targeting FPGA on chip memory but you can replace it with DDR3 or DDR4.
Thanks.
Regards,
dlim
