PCIe + DMA project on DB4CGX15

Hi all,

I'm new in PCIe developing and want your help.

I'm using DB4CGX15 evaluation board from DevBoards.

I need to transfer data from outside to PC. The data is 32 bits width and clock is 85 MHz.

Amount of data may vary from 150Mbytes up to unknown.

DB4CGX15 is using PCIe x1 configuration, but the final project will support PCIe x2 Gen1.1.

The main idea of the project is to use Hard IP core for PCIe and SGDMA with FIFOs.

The QSYS system contains:

• PCIe IP core

• SGDMA (32bits) with enabled packet transfers

• Avalon-ST dual clock FIFO (32 bits) with packet transfers

• PIOs for registers (connected to BAR0)

Quartus (12.1) contains:

• QSYS compiled block

• PLLs

• Dual clock FIFO for clock synchronization

What i have tried and succeeded: I have connected only 8 bit data stream with 60MHz clock to first FIFO (in quartus). Output of FIFO is 32 bits with 30MHz clock has connected to Avalon-ST dual clock FIFO.

This system has worked successfully. When i raised stream clock to 85 MHz, i received broken data (for example some bytes in a middle of a data were missing).

Now i want to receive 32 bits of data stream. My suggestion is to use several SGDMA controllers (2 or 4) and put them in queue reading.

Does anyone has better suggestion for my project?

Another problem that i can't fully understand is a principle of work of Avalon-ST FIFO. I have built controller to control signals like start of packet/end of packet/ready/valid/empty but still not sure that my controller is working properly.

I found documentation for this FIFO, but there is no any explanation for correct sequence of signals.

Any help will be appreciated.