Hi - so I just got my first Altera Development kit (S-IV GX S530). My "hello world" project starts with a tiny user-designed design (i.e. RTL code) that I download to the board that consists of some registers. I want to have a simple PC interface that allows me to read/write these registers on the FPGA on the development board from the PC. It can be a command-line interface (I can later put a GUI on top of it). I'm guessing/hoping that the building blocks for this structure exist and I just have to paste them together. (PC-based USB driver -> USB interface on FPGA, or maybe Rj45 Ethernet?) Can anyone point me in the right direction? Much Thanks! /j

--- Quote Start --- I'm guessing/hoping that the building blocks for this structure exist and I just have to paste them together. (PC-based USB driver -> USB interface on FPGA, or maybe Rj45 Ethernet?) Can anyone point me in the right direction? --- Quote End --- The JTAG interface can be used to implement communications. However, you are then limited to using Altera applications on the host. This is not too much of a pain for simple tests, but it does get annoying. I'm looking into a better solution and will post my results. Start by using an Avalon-MM JTAG master along with the SystemConsole Tcl functions to access the device. Design your custom logic as an Avalon-MM slave device. If you use the RJ45 interface, then you'll need a network interface controller. There is an Altera TSE IP core, but I have yet to test it. I'm not sure how much work it would be to code your own. Once you have the ethernet connected as an Avalon-MM/ST device, then you can code up a server on a NIOS II processor. This would provide a higher-bandwidth interface. If you have the board plugged into a PCIe motherboard, then you can use a PCIe-to-Avalon-MM bridge IP core, and then communicate from the host as if the board is a PCI device. This is simple under Linux, and you can probably use the Jungo driver under Windows. I have the same kit as you, but with the 230 devices. I've been using JTAG for testing up until now, but the ethernet and PCIe tests are on my TODO list. If you get stuck, ask, and I'll help if I can. Cheers, Dave

Hi Dave - that's a start - thanks!. Can higher level applications (like LabView) talk to the Altera application on the host? /j

Also - something about your explanation confuses me. I think you're telling me to put the Avalon-MM JTAG Master device on the FPGA as a piece of IP, and design my logic as an Avalon slave. So far so good, but I don't quite understand the path from the JTAG Master IP on the FPGA to the PC - will it "bind" to the JTAG port automatically? What SW App do I run on the PC to get a command-line interface to it? If there's like, a good tutorial on this (or a few manual section), I'm game to RTFM. Thanks very much! /j

--- Quote Start --- Can higher level applications (like LabView) talk to the Altera application on the host? --- Quote End --- Not without a little extra work. There are effectively two separate methods to create JTAG interfaces; low-level access via the Virtual JTAG IP core, and access via SOPC Builder components such as the JTAG to Avalon-MM master bridge. Both of these IP components come with a corresponding set of Tcl procedures. The Tcl procedures access the JTAG interface via DLLs with unpublished APIs. There are posts explaining how to use some of these directly, but I have not tried this. I've used both the Virtual JTAG and Avalon-MM IP cores. I'd recommend playing with the Avalon-MM IP first. Using Qsys or SOPC Builder, create a system with a JTAG to Avalon-MM master, a RAM block, and a GPIO block, and use SystemConsole Tcl commands to access this system. I recall a fairly decent webinar on the topic ... perhaps it was one of these http://www.altera.com/support/examples/on-chip-debugging/on-chip-debugging.html Have a look at that stuff, and if it becomes too confusing, I'll create a design and some scripts for you to play with. Back, to your original question; Labview cannot talk to any of these IP cores directly, since the access is via a console in an Altera application. However, you can write a Tcl server, start that using the appropriate quartus command-line tool and then use sockets from Labview. Not ideal, but not too ugly either. Cheers, Dave

--- Quote Start --- I don't quite understand the path from the JTAG Master IP on the FPGA to the PC - will it "bind" to the JTAG port automatically? What SW App do I run on the PC to get a command-line interface to it? If there's like, a good tutorial on this (or a few manual section), I'm game to --- Quote End --- Its all about knowing the right terminology, eh. Look in the Quartus Handbook at System Console. This tool is a Tcl console with Tcl procedures that can be used to find your device on the JTAG chain, and then send read/write commands. The Virtual JTAG interface is accessed from a different tool, quartus_stp, with different Tcl procedures. Start with System Console, as this seems like the tool Altera wants you to use. Cheers, Dave

PC <-> S530Dev. Bd. Reg R/W interface? | Altera Community

33 Replies

Altera_Forum
Honored Contributor
14 years ago
Dave,

Jeff and I appreciate your suggestions for interfacing LabVIEW to the System Console. Per your suggestion, I've started down the path of implementing a Tcl server application within the System Console using Tcl's standard networking functions. I've noticed that the "fileevent" Tcl command, which is commonly used for receiving socket data on an event-driven basis, doesn't seem to be recognized by the System Console's interpreter. In your experience, does System Console only support a subset of the standard Tcl commands? We were looking for documentation on which standard commands were supported, but had no luck. Thanks.
Altera_Forum
Honored Contributor
14 years ago
Hi,

--- Quote Start ---

Jeff and I appreciate your suggestions for interfacing LabVIEW to the System Console. Per your suggestion, I've started down the path of implementing a Tcl server application within the System Console using Tcl's standard networking functions. I've noticed that the "fileevent" Tcl command, which is commonly used for receiving socket data on an event-driven basis, doesn't seem to be recognized by the System Console's interpreter. In your experience, does System Console only support a subset of the standard Tcl commands? We were looking for documentation on which standard commands were supported, but had no luck. Thanks.
--- Quote End ---
I've noticed that Altera has managed to screw up the System Console Tcl interpreter in other ways too ...

Here's a snippet of code I use to detect the Tcl shell type

# Tool (wish shell) detection set toolname ] if { == 0} { # Toolname starts with 'wish' set tool wish } elseif { == 0} { # Modelsim starts vish.exe # (alternatively argv0 ends in vsim) set tool modelsim } elseif { == 0} { # Quartus also has a global called quartus # that can be detected using . set tool quartus # Quartus shells need to initialize Tk init_tk } else { error "Tcl/tk tool detection failed!" }
Start 'quartus_stp -s' and

tcl> info nameofexecutable C:/software/altera/10.1/quartus/bin/quartus_stp.exe tcl>
The above code snippet allows the display of Tk GUI elements when using quartus_stp, or the main Quartus GUI.

However, I tried this in SystemConsole (Quartus v10.1) and the result of 'info nameofexecutable' is an empty string! On top of that, the TK widgets don't work (try typing tk_init, or help misc)!

I get the impression that at Altera there are two different software development groups, and neither has bothered to talk to the other to ensure compatibility between tools.

So, my recommendation is to use SystemConsole with caution (I know, I recommended looking at it ... sorry, I was too optimistic). The quartus_stp tool is reliable, but I'm not sure that the SystemConsole commands work there. They can be made to work, its just that I'm not sure that Altera provides a package with the Tcl commands. The majority of USB interfaces I have built up until now have used the Virtual JTAG interface, and I control that via quartus_stp.

All is not lost. I've figured out how to communicate with the USB-Blaster directly from C/C++ code. In the next week or so, I'll finish documenting how to do this, and then I was going to put together a DLL that could be accessed from LabView code. This documentation would include HDL code for USB-to-Avalon-MM masters, so you can replace the components and Tcl interfaces provided by SystemConsole, with something you are free to change.

You're welcome to be a guinea pig for that code :)

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Thanks Dave - we look forward to it!
/j

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PC <-> S530Dev. Bd. Reg R/W interface?

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