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The JPEG algorithm has 4 main blocks, DCT, Quantization, Entropy, and Huffman Coding.
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First of all, you need to be sure which parts of your design is fixed, and which parts you want them to be reconfigurable.
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1. Does this mean I can't implement the JPEG algorithm in HDL because I'm not actually going to reconfigure the hardware?
2. If I am not going to reconfigure hardware then from what I understand, I will implement a design that will behave in multiple ways according to a configuration that it is set to, pretty much like a microcontroller?
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Next, for the reconfigurable parts of your design, try to determine a "language" or "syntax" of the configuration bits in general. Yes. it is very pretty much like a microcontroller (you can have your own simple assembly language or something, or define your own protocol). Try to make the configurable parts of your design to follow some "sequence" (like assembly coding), and you can "change the sequence" however you like (similar to assembly, where you can also change the sequence).
You can then "scan in" this sequence through the said interface (I'll call this interface "PC Interface" from now on - can be USB, RS232, etc.), and let your "soft reconfiguration controller" decide how to process that new sequence - probably turn off some blocks, or set some blocks to high-speed mode, or change the buswidths of some blocks to a smaller value (this of course you'd need to define a maximum buswidth in your HDL), or whatever you need.
I'm not too sure of the details of your image processing project. But let's say you have 2 different implementations (different algorithms) for DCT, and 3 different algorithms for Quantization, and the other two blocks (entropy and Huffman Coding) are fixed. Then I'd suggest that you find out the differences between your different algorithms. Use these differences to determine which of the two implementations you want to run at any one time (these are your settings).
Here is one simple example (does not use the "sequence" method earlier), but uses multiplexers to choose between algorithms (already compiled as separate blocks into the FPGA):
Say, between DCT1 and DCT2, you have 1 term that's different, and the other terms are the same between the 2 algorithms. You can have a setting, maybe "DCT1" to choose the DCT1 algorithm, and "DCT2" to choose DCT2. You scan this (either "DCT1" or "DCT2") from your PC interface into your "soft reconfiguration controller". For example, after scanning "DCT1", your soft controller tells your DCT block to take the result using the term specifically meant for the DCT1 algorithm.
Another way using the "sequence method" (this is probably harder, but could save you a lot of logic resources - this behaves a bit like a microcontroller):
Write a generic DCT equation that can cater for both DCT1 and DCT2 algorithms in HDL. Similarly write a generic equation for the Quantization block that is able to support all your quantization techniques.
Scan in the detailed equations from the PC interface and let your logic implement those equations.
I've never done this before, but I believe this can be done... you just need some time to think.
Tip: what I can think of now is implement multipliers, adders, comparators, and dividers, but your HDL doesn't know the exact algorithm yet until it receives the detailed equation. It doesn't know 'what multiplies what', or 'what adds to what', etc. After it receives your detailed algorithm, will it decide how to properly use those blocks. Sounds like making your own scientific calculator, no? Here of course, you need to reserve a "maximum" number of multipliers/adders/etc. for your implementation.
Well, just my thoughts... not perfect though.
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