Honored Contributor
Honored ContributorHi!
First of all, thank you so much for your replies. I have a few questions :) 1. --- Quote Start --- It is something like having the whole scan chain designed yourself, instead of using Altera's partial reconfiguration hard circuitry on silicon. --- Quote End --- Regarding the quote above, Does this mean I can't implement the JPEG algorithm in HDL because I'm not actually going to reconfigure the hardware? 2. If I am not going to reconfigure hardware then from what I understand, I will implement a design that will behave in multiple ways according to a configuration that it is set to, pretty much like a microcontroller? 3. My JPEG algorithm is about 40k LEs if it is implemented in HDL, my NIOSII controller is aroudn 9k and I will have other peripherals implemented. This means that I have to limit the JPEG block (which is the configurable design block). Then the HDL I will load into this block is a set of logic blocks that the whole JPEG algorithm needs but not in a way that the whole algorithm is implemented. To explain further: The JPEG algorithm has 4 main blocks, DCT, Quantization, Entropy, and Huffman Coding. These cannot fit in the FPGA as they are thus the need for the configurable design. So, from what I understand, I will implement a design that have elements that cater to all of these blocks but does not act as the JPEG algorithm right away. Then the configuration bits or "settings" will choose how the circuit will behave, first as the DCT, then after change the settings as the other blocks. Is this right? 4. --- Quote Start --- Please notice, that the original poster asked for reconfiguration because the full application functionality doesn't fit the FPGA resources. In this case "soft reconfiguration" isn't an option, because it can't but switch between blocks that have been compiled to the FPGA image before. --- Quote End --- Does my question# 3 pertains to this issue? Is switching between blocks different from reconfiguring the behaviour of the circuitry, like how I described the system in question# 3? 5. --- Quote Start --- I would prefer the term configurable design for the feature. But because alternative logic functionality most be provided and configuration registers in addition, it has an increased resource demand compared to fixed application specific designs. --- Quote End --- I don't quite understand the alternative logic funcionality and configuration registers here... How do they work? Thanks again :)
