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HSuh01's avatar
HSuh01
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Our host PC can't discover Stratix 10 MX devkit as a PCIe device, even after a successful configuration and a proper installation of Linux driver.

We are trying to use Intel's DMA IP and PCIe Hard IP+ to communicate to the HBM memory. So far, we've tested AN881 design, AVMM PCIe Hard IP+ example design, and the PCIe golden design that comes wit...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    6 years ago

    Hi Hsuh,

    The initial post was mention about AN811 but now become AN881. So I just curious if you already tested the AN881.

    1. For the AN881 example design, it is using v19.1 pro. Did you run the Post-processing Script (section 2.2) if you re-generate the Platform designer or upgrade the design?
    2. Is your MX board consist of the following device? 1SM21BHU2F53E1VG
    3. Are you using the driver that comes with the AN881 example design?
    4. Do you have a chance to validate it on the CentOS 7.0 and see if there is any OS dependency?
    5. Could you please capture ltssmstate[5:0], currentspeed[1:0], lane_act[4:0] and link_up signal from Signaltap? This can help to confirm if the link training is up correctly.

    Regards -SK

SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi

We tested the design by using 1SM21BHU2F53E1VG in the past, and it can link up properly. This is a production device that same with the device in this link: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-mx.html

The 1SM21BHU2F53E2VGS1 is the engineering sample device, and the board is currently not available for testing.

When you generate the example design by using the PCIe IP AVMM GUI, did you select "Stratix 10 MX H-Tile ES1 FPGA Development Kit"? Did you able to try it by using a different server/host?

Besides, you may also try to use "Avalon ST Intel Stratix 10 hard IP for PCI express" or "Avalon-MM Intel Stratix 10 Hard IP for PCIe Express" from IP catalog to generate the example design and see if it can link up as Gen3X8 as expected and detect by the host. This can help to rule out if there is a design example dependency.

Regards -SK

Regards -SK