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HSuh01's avatar
HSuh01
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6 years ago
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Our host PC can't discover Stratix 10 MX devkit as a PCIe device, even after a successful configuration and a proper installation of Linux driver.

We are trying to use Intel's DMA IP and PCIe Hard IP+ to communicate to the HBM memory. So far, we've tested AN881 design, AVMM PCIe Hard IP+ example design, and the PCIe golden design that comes wit...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    6 years ago

    Hi Hsuh,

    The initial post was mention about AN811 but now become AN881. So I just curious if you already tested the AN881.

    1. For the AN881 example design, it is using v19.1 pro. Did you run the Post-processing Script (section 2.2) if you re-generate the Platform designer or upgrade the design?
    2. Is your MX board consist of the following device? 1SM21BHU2F53E1VG
    3. Are you using the driver that comes with the AN881 example design?
    4. Do you have a chance to validate it on the CentOS 7.0 and see if there is any OS dependency?
    5. Could you please capture ltssmstate[5:0], currentspeed[1:0], lane_act[4:0] and link_up signal from Signaltap? This can help to confirm if the link training is up correctly.

    Regards -SK

HSuh01's avatar
HSuh01
Icon for New Contributor rankNew Contributor
6 years ago

I got the results. But I am worried about these results because it clearly shows that the design is not working properly.

Formerly, when I posted former result, that came from slot 1 ~ slot 4 by using Signal Tap, I thought at least slot 1 and 2 is working as you specified in your last answer.

However, It turns out that those results were not correct. When I did those tests, I reboot host PC to enumerate FPGA board, I didn't do complete power-off and on.

Today, while I was performing test, I powered off host PC completely and turned it on again for enumeration. I found that all 4 slots (PCIe slot 1 through 4) is not working.

Please see the attached screenshots for the results I got.

1.Right after the PC is powered on, it's in gen1 x16 state and ltssm shows 00h.

2. After a few second, state changes but still PCIe link is not up.

3. Also, sometimes, our PC does not boot up. It just stays on the black screen. Nothing special or different could be found in Signal Tap status when this happens (the same as above two screenshots).

The weird thing is, when I stop data acquisition in the Signal Tap, it shows ltssm = 11h, currentspeed = 03h, lane_act = 10h and link_up = 1. Which are clearly what we want to see.

This occurs randomly.

Also, I have a request for you. I have a very good reason to believe that PCIe HARD IP+ is not working in our environmental settings (Quartus 19.2 with a device variant 1SM21BHU2F53E2VGS1). When I synthesize PCIe HARD IP+, I am getting multiple timing errors in the main IP itself, not in the interconnect between modules and IPs.

Could you test this design, AN881, on the ES variant of Stratix 10 MX(1SM21BHU2F53E2VGS1)? Please do not test this design on the 1SM21BHU2F53E2VG (which was clearly used in the development stage only for the internal use at Intel).

If you could successfully run the this design, please let me know what Linux distro, Quartus version, and Linux driver was used. I will try to replicate it on my side. If you can share me the bitstream that is used for FPGA configuration(.sof file) that will be greatly helpful.