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HSuh01's avatar
HSuh01
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Our host PC can't discover Stratix 10 MX devkit as a PCIe device, even after a successful configuration and a proper installation of Linux driver.

We are trying to use Intel's DMA IP and PCIe Hard IP+ to communicate to the HBM memory. So far, we've tested AN881 design, AVMM PCIe Hard IP+ example design, and the PCIe golden design that comes wit...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    6 years ago

    Hi Hsuh,

    The initial post was mention about AN811 but now become AN881. So I just curious if you already tested the AN881.

    1. For the AN881 example design, it is using v19.1 pro. Did you run the Post-processing Script (section 2.2) if you re-generate the Platform designer or upgrade the design?
    2. Is your MX board consist of the following device? 1SM21BHU2F53E1VG
    3. Are you using the driver that comes with the AN881 example design?
    4. Do you have a chance to validate it on the CentOS 7.0 and see if there is any OS dependency?
    5. Could you please capture ltssmstate[5:0], currentspeed[1:0], lane_act[4:0] and link_up signal from Signaltap? This can help to confirm if the link training is up correctly.

    Regards -SK

SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi ,

The PCIe is failed to link up at slot 4. This is why the host can't detect it.

Here is the result that I can see from your post:

Slot 1: Link up with Gen3 x 4

Slot 2: Link up with Gen3 x 4

Slot 3: Failed to link up

Slot 4: Failed to link up

After the program the sof file to the FPGA, when the host performs a warm reboot, the perst will trigger by the host, and then it will reset the FPGA and restart the link training. When you capture the signal tap, please set the trigger condition as the rising edge of "pin_perst" signal. This can help to confirm if the FPGA gets reset properly during warm reboot.

Regards -SK