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HSuh01's avatar
HSuh01
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6 years ago
Solved

Our host PC can't discover Stratix 10 MX devkit as a PCIe device, even after a successful configuration and a proper installation of Linux driver.

We are trying to use Intel's DMA IP and PCIe Hard IP+ to communicate to the HBM memory. So far, we've tested AN881 design, AVMM PCIe Hard IP+ example design, and the PCIe golden design that comes wit...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    6 years ago

    Hi Hsuh,

    The initial post was mention about AN811 but now become AN881. So I just curious if you already tested the AN881.

    1. For the AN881 example design, it is using v19.1 pro. Did you run the Post-processing Script (section 2.2) if you re-generate the Platform designer or upgrade the design?
    2. Is your MX board consist of the following device? 1SM21BHU2F53E1VG
    3. Are you using the driver that comes with the AN881 example design?
    4. Do you have a chance to validate it on the CentOS 7.0 and see if there is any OS dependency?
    5. Could you please capture ltssmstate[5:0], currentspeed[1:0], lane_act[4:0] and link_up signal from Signaltap? This can help to confirm if the link training is up correctly.

    Regards -SK

HSuh01's avatar
HSuh01
Icon for New Contributor rankNew Contributor
6 years ago

I got the result. Seems like we can't set up the link in gen3 x16. These are the screenshot of Signal Tap analyzer for ltssm, link_up, currentspeed, etc.

THIS IS A SIGNALTAP INFO FOR AN881 EXAMPLE.

THE DEVICE IS ON PCIE SLOT4.

The signal keeps changing sequentially, which doesn't seem correct, or doing something meaningful inside of it. Signal sequence looks like this.

ltssmstate : 00h 08h 00h 08h 08h 00h 08h 00h 08h 00h 02h

currentspeed : 1h 1h 1h 1h 1h 1h 1h 1h 1h 1h 1h

lane_act : 10h 10h 10h 04h 10h 10h 10h 10h 10h 10h 10h

link_up : 0(always)

In this test, the FPGA board is in gen1 x16 state, but link is not setup.

We also tested FPGA board in other slots but it was not successful. We've tested from slot1 (direct connect to the CPU) to slot4. We couldn't test slot5 because there is no space that can fit the height of FPGA board in to the host PC's casing.

(slot5 is not a PCI slot. we have slot6 which is a PCI slot.) According to the manufacturer of the motherboard, we can use either slot2 or slot4 for full lane PCIe communiation(16 lane)

These are the test result from other slots. There was no transition in values like we had in slot4.

slot1 : (can't pass BIOS POST. Not bootable host PC) signaltap says ltssm(11h), currentspeed(03h), lane_act(04h), link_up(1)

slot2 : (booting of PC was successful) ltssm(11h), currentspeed(03h), lane_act(04h), link_up(1)

slot3 : (bootable) ltssm(h03), currentspeed(01h), lane_act(01h), link_up(0)

I have been thinking about it and I think FPGA board needs to be reset (without losing configuration) and need to kick in everything when host PC is powered up. I think PCIe IP just pass through initial handshaking status after bitstream(.sof) configuration.

Since FPGA board is now powered on with separate power supply(Intel's power), some sort of reset might do this. Do you have any suggestion? Or do you know what's happening on FPGA?

Thank you

Regards,

HSuh.

P.S. : This is our BIOS screenshot. Our host PC doesn't even see FPGA board as a PCIe device. As I said, it's currently sitting in slot4.

(This screenshot is taken after a configuration and after an enumeration.)