Our host PC can't discover Stratix 10 MX devkit as a PCIe device, even after a successful configuration and a proper installation of Linux driver.

Hi, SK.

I got a result from AN881 example design. I changed power supply to the one that comes with the Stratix 10, but it's still not working. Though, I think we need to use them, because when a host PC detects FPGA card, it enumerates the device list during POST and power will be reset once or twice. This power reset will erase FPGA configuration if the board is powering from the PSU of host PC.

Also, I tried to capture ltssmstate[5:0], currentspeed[1:0], lane_act[4:0] and link_up signals, but it was not successful. Is there any specific way to make it visible in the design? I know the original PCIe Hard IP+ has these signals, and I also turned on "Enable hard IP status bus when using AVMM interface," but the signals are still not visible.

So, I tried to turn on PCIe inspector by turning on PCIe instpector related options in IP parameter editor through Configuration Debug, and Extension options tab. However, it is getting errors with AN881 example design. (PFA. I attached screenshot for this.)

To find out what's causing the problem, I created an example design of original PCIe HARD IP+, and I got a PCIe test result from PCIe inspector. (Also attached this to the post). But I still can't see ltssm, currentspeed, etc. signals on the top level. I am experiencing these two problems.

1. ltssmstate, currentspeed, lane_act signals are not active and not exist.
2. signaltap node finder is not working. Even if there is signals, I can't search any node. I tested it with signals that confirmed as exist. It always says "no nodes found." I set "pcie_example_design.qsys" as a top in Quartus.

Is there any specific way to make those debug signals visible? Instead, I got you a result from PCIe inspector. THIS RESULT IS FOR PCIE HARD IP+'S EXAMPLE DESIGN. NOT FROM AN881.

Thank you.

Regards, Han.