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HSuh01's avatar
HSuh01
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6 years ago
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Our host PC can't discover Stratix 10 MX devkit as a PCIe device, even after a successful configuration and a proper installation of Linux driver.

We are trying to use Intel's DMA IP and PCIe Hard IP+ to communicate to the HBM memory. So far, we've tested AN881 design, AVMM PCIe Hard IP+ example design, and the PCIe golden design that comes wit...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    6 years ago

    Hi Hsuh,

    The initial post was mention about AN811 but now become AN881. So I just curious if you already tested the AN881.

    1. For the AN881 example design, it is using v19.1 pro. Did you run the Post-processing Script (section 2.2) if you re-generate the Platform designer or upgrade the design?
    2. Is your MX board consist of the following device? 1SM21BHU2F53E1VG
    3. Are you using the driver that comes with the AN881 example design?
    4. Do you have a chance to validate it on the CentOS 7.0 and see if there is any OS dependency?
    5. Could you please capture ltssmstate[5:0], currentspeed[1:0], lane_act[4:0] and link_up signal from Signaltap? This can help to confirm if the link training is up correctly.

    Regards -SK

HSuh01's avatar
HSuh01
Icon for New Contributor rankNew Contributor
6 years ago

This is answers to your question.

  1. No. Are you referring scripts that comes in the form of zip archive? We updated IPs so that it can be matched with Quartus19.2
  2. Our device variant is 1SM21BHU2F53E2VGS1 not just E1VG. This is a ES variant.
  3. Yes. It is compiled currectly and loaded before we run any test. (We load the driver again if the host is restarted)
  4. No. I can try, but our IT policy allows us to use specific Linux distribution. We are using NFS system.
  5. I will get back to you once I got the signal tap results.