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HSuh01's avatar
HSuh01
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6 years ago
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Our host PC can't discover Stratix 10 MX devkit as a PCIe device, even after a successful configuration and a proper installation of Linux driver.

We are trying to use Intel's DMA IP and PCIe Hard IP+ to communicate to the HBM memory. So far, we've tested AN881 design, AVMM PCIe Hard IP+ example design, and the PCIe golden design that comes wit...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    6 years ago

    Hi Hsuh,

    The initial post was mention about AN811 but now become AN881. So I just curious if you already tested the AN881.

    1. For the AN881 example design, it is using v19.1 pro. Did you run the Post-processing Script (section 2.2) if you re-generate the Platform designer or upgrade the design?
    2. Is your MX board consist of the following device? 1SM21BHU2F53E1VG
    3. Are you using the driver that comes with the AN881 example design?
    4. Do you have a chance to validate it on the CentOS 7.0 and see if there is any OS dependency?
    5. Could you please capture ltssmstate[5:0], currentspeed[1:0], lane_act[4:0] and link_up signal from Signaltap? This can help to confirm if the link training is up correctly.

    Regards -SK

HSuh01's avatar
HSuh01
Icon for New Contributor rankNew Contributor
6 years ago

Hi, SengKokl.

I am sorry about my former post. I didn't know that you read my former post. I just checked my post frequently to make things clear. I thought that way a reader can grasp what's going on on my side easily.

Sorry for the confusion and for my attitude.

I will try to test your suggestions. Allow me to take some of my time because our server is located in the datacenter. To do the test you mentioned above, we need to once get the host server back to our office.

Meanwhile, could you tell me if there is a way to check that the settings(BIOS, physical slot placement on the motherboard, PCIe generation mode settings, etc.) on the host server is correct?

Since we don't know what's causing the problem right now, there is a chance that both FPGA configuration bitstream(.sof file) and the host server setting are wrong.

Currently, our FPGA is sitting on the x16 PCIe lane (gen 3.0) and we verified that the slot has full speed access to the host.

ASPM(Active State Power Management) level is disabled so that we can have full compatibility on any PCIe device.

Also, 4G decoding or Memory Mappinng of IO above 4GB is enable for the same reason. ( It allow 64bit PCI devices to be decoded above 4GB address space.)

Thank you,

Hsuh.