Onchip Memory Simulation

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Hi,

I'm simulating an onchip memory access through Avalon. When my master logic sends a read request, the readdatavalid (I'm doing a pipelined read) is set properly by the controller. The problem is, the readdata line is all X! It never goes through a transition ever! I'm simulating with Modelsim-Altera free version. Thanks for any help,

Just to have said, modelsim does give me some warnings about some unconnected ports for the onchip module, but I've created the design by SOPC, so I guess it shouldn't matter, right?! :)

Kaveh

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Do you mean that you have an on-chip memory created in the SOPC Builder? Or you have your own design of on-chip memory that is outside the SOPC system and you are communicating with the Avalon bus through an "interface" component? Please also write how are you simulating your system. I believe you have embedded your test-bench in the Simulation file generated by the the SOPC system.

I'm using the on-chip memory (SRAMs). Anyways, I remember I got it to work by setting a parameter in the verilog file that SOPC creates. Unfortunately, I don't remember exactly which parameter it was that I had to change. I think the "init_file" parameter was set incorrectly by SOPC that I had to set it myself.

Thanks,

Kaveh

I think what you are failing to mention is that you expect the RAM to have been initialized with some data before the simulation.

Try this:

http://www.altera.com/literature/an/an189.pdf