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Altera_Forum
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17 years ago

Onchip Memory Simulation

Hi, I'm simulating an onchip memory access through Avalon. When my master logic sends a read request, the readdatavalid (I'm doing a pipelined read) is set properly by the controller. The prob...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I'm using the on-chip memory (SRAMs). Anyways, I remember I got it to work by setting a parameter in the verilog file that SOPC creates. Unfortunately, I don't remember exactly which parameter it was that I had to change. I think the "init_file" parameter was set incorrectly by SOPC that I had to set it myself.

Thanks,

Kaveh