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Honored Contributor
Honored ContributorOnchip Memory Simulation
Hi, I'm simulating an onchip memory access through Avalon. When my master logic sends a read request, the readdatavalid (I'm doing a pipelined read) is set properly by the controller. The prob...
Altera_ForumHonored Contributor
Honored ContributorI think what you are failing to mention is that you expect the RAM to have been initialized with some data before the simulation.
Try this: http://www.altera.com/literature/an/an189.pdf
