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Altera_Forum
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18 years ago

Onchip Memory Simulation

Hi, I'm simulating an onchip memory access through Avalon. When my master logic sends a read request, the readdatavalid (I'm doing a pipelined read) is set properly by the controller. The prob...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

What do you expect to come out of the RAM? Is the RAM completely initialized with some meaningful content? Otherwise the X would be correct.