Onboard clock issue

Question

Hi all,

I'm trying to learn on how to access the onboard peripherals of the Cyclone 2 Starter kit and having difficulties finding a simple example on how to use one of the available onboard 3 clocks (24Mhz, 27Mhz, 50Mhz) of the Cyclone 2 Starter Kit using pure VHDL coding. I do not want to use PLL, external clocks, I only want to use just one of the 3 available onboard clocks.

For example, let say I have the following coding snippet, how do I do to let's say connect the onboard 50 Mhz clock to drive the clock_in input pin of the counter? - I know it's called CLOCK_50 and I have to declare that name in the entity. It does matter what mode I declare that name, I keep receiving an error message, as if there's nothing to be done! :mad:

Can anybody help to concretise a very simple working example on using onboard crystal clocks? - By the way, the onboard FPGA is an ep2c20f484c7.

entity counter is

port(

clock_in : in std_logic;

clock_out : out std_logic

);

end counter;

architecture behavior of counter is

begin

process(clock_in)

variable count_var : integer;

begin

count_var := 0;

-- Some code here ...

clock_out <= count_var;

end process;

end behavior;

Regards,

altera_forum · Answer

Hey

I am not sure if you are messing up with basics...

Dont overthink.. I believe its pretty straight forward

and simple.

Lets asuume your Top file is top_entity and

your have a entity with a clock input.

Ex: entity top_entity is

port (

CLOCK :IN STD_LOGIC;

--Your other Port declarations

);

end top_entity;

--Your Architecure and the logic design follow

Just compile this top file of yours

make sure you have no errors..

Once done go to assignments->Pin assignments

Check up your schematic to know the pin number

to which your say 50MHz is connected.

In Pin assignments just assign that pin number

to your entities CLOCK.

This is all I guess.....

I hope this is what you were strugling with...

altera_forum · Answer

Hi again,

I've done that, and yet nothing. The code compiles ok. To clear the mess, tomorow I'll write a small counter program and try to drive it's clock input to one of the three onboard clocks. Maybe I'll find my way with a couple of lines program.

As if it was not enough already enough complicated, according to the board specs, these clocks are inputs unstead of outputs. So how can inputs drive other inputs? - The clock names are CLOCK_24, CLOCK_27 and CLOCK_50.

Thanks,

altera_forum · Answer

Hi If possible upload your project. State your needs clearly. Let me see what could be done.

altera_forum · Answer

Hi,

--- Quote Start ---

As if it was not enough already enough complicated, according to the board specs, these clocks are inputs unstead of outputs. So how can inputs drive other inputs? - The clock names are CLOCK_24, CLOCK_27 and CLOCK_50.

--- Quote End ---

These 3 clocks (CLOCK_24, CLOCK_27 and CLOCK_50 are input clocks to the FPGA. So you can use them as input clock for your HDL design module, which connects to the respective FPGA clock pin, i.e., your module clock input pin gets clock from one of these FPGA clock input pins. So if you want to use CLOCK_24 input for your counter module, assign pin A12 or B12 in the pin assignments of your Quartus II project. If you want to use CLOCK_27 input for your counter module, assign pin E12 or D12 in the pin assignments of your Quartus II project. If you want to use CLOCK_50 input for your counter module, assign pin L1 in the pin assignments of your Quartus II project and perform full compilation of your project. The generated sof/pof file should work for you as per your expectation.

Hope this helps.

BD

altera_forum · Answer

Hi,

Thanks for answering. I do beleive you and jmaniac are right. There's one think I did'nt

check yet and I'm sure the mistake is there. I've manually created a .csv a pin assigment file and I'm sure now that many mistakes could be done at 3 o'clock in the morning doing that kind of assigment. I've Probably did a wrong pin name entry or a wrongly named a symbolic name. Probably named CLOCK_50 as CLOCK50 for example. Thanks to you also, I've realized that this file is automatically done and should as mine be imported instead being done manually.

As of this morning, I can now see happy smiling corean investors :cool: coming in to see the demo demond machine, while me and my terrified friends engineers folks happy to learn that they will still be around at least up to the next project; not to forget my boss now happy enough to spread the good words about Altera and probably buy 100 of their products for the next ten years; hoppefully if we're still around.

I'll let you know...

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Onboard clock issue

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