Onboard clock issue

Hi,

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As if it was not enough already enough complicated, according to the board specs, these clocks are inputs unstead of outputs. So how can inputs drive other inputs? - The clock names are CLOCK_24, CLOCK_27 and CLOCK_50.

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These 3 clocks (CLOCK_24, CLOCK_27 and CLOCK_50 are input clocks to the FPGA. So you can use them as input clock for your HDL design module, which connects to the respective FPGA clock pin, i.e., your module clock input pin gets clock from one of these FPGA clock input pins. So if you want to use CLOCK_24 input for your counter module, assign pin A12 or B12 in the pin assignments of your Quartus II project. If you want to use CLOCK_27 input for your counter module, assign pin E12 or D12 in the pin assignments of your Quartus II project. If you want to use CLOCK_50 input for your counter module, assign pin L1 in the pin assignments of your Quartus II project and perform full compilation of your project. The generated sof/pof file should work for you as per your expectation.

Hope this helps.

BD