niosii ethernet std design 3c25 neek critical warnings

Hi,

When I build the NIOS2 Ethernet Standard Design for the 3C25 Neek I see some critical warnings (see below), and I was curious if there are any patches available for this issue, or perhaps there is someplace I can obtain the missing 'sdram_phy_ddr_timing.sdc' file?

Also, when I write, and then read back, the SGDMA control registers using the base address in the generated file 'system.h', I don't appear to successfully modify this register. Closer examination reveals that the macro ETHERNET_SUBSYSTEM_SGDMA_TX_BASE specifies a base address of 0x800a440. In QSYS I see that the "ethernet_subsystem.ethernet_bridge" is at 0x800a000-0x800a7ff and that in the ethernet subsystem "sgdma_tx.csr" is at 0x440-47f. So that probably indicates that QSYS is reporting also the same base address, and therefore I am pretty clueless as to why the register isn't responding in code and also when manipu;lating it in gdb. I do use code like this for accessing the memory mapped registers bypassing the cache (which does work for example with the Altera TSE registers).

static inline uint32_t ioRead32 ( const uint32_t * const pSrc )

{

return __builtin_ldwio ( ( void * ) pSrc );

}

static inline void ioWrite32 ( uint32_t * const pDest, const uint32_t newVal )

{

__builtin_stwio ( pDest, newVal );

}

Critical Warning: No exact pin location assignment(s) for 1 pins of 113 total pins

Info: Pin flash_a[0] not assigned to an exact location on the device

Critical Warning: Synopsys Design Constraints File file not found: 'sdram_phy_ddr_timing.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

Critical Warning: Synopsys Design Constraints File file not found: 'sdram_phy_ddr_timing.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

Critical Warning: Timing requirements not met

Critical Warning: Timing requirements not met

Critical Warning: Timing requirements not met