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Altera_Forum
Honored Contributor
14 years agoStill stuck attempting to resolve this error (which prevents timing from being made).
Critical Warning: Synopsys Design Constraints File file not found: 'sdram_phy_ddr_timing.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. I am using the ethernet standard design unmodified. The file in question does exist under a different name - eth_std_main_system_sdram_phy_ddr_timing.sdc. When I search the entire design I find only this in a hif file. This file _does_ exist so I don't know how to proceed. lib_eth_std_main_system eth_std_main_system|synthesis|submodules|eth_std_main_system_sdram_phy_ddr_timing.sdc lib_eth_std_main_system