NIOS Reset Button Not working in Max10 Kit

I am working with max 10 fpga development kit (https://cloud.altera.com/devstore/board/max-10-fpga-development-kit/) and demo of Nios II Simple Socket Server Ethernet Example.

SSS works well after changing few things ( Flash address definition ).

But I could not reset NIOS by pressing CPU_RESETn on KIT.

Another question：

in the "m10_rgmii.v", why they use user_pb[0] ?

BTW: When I use simple QSYS demo (without ETH, DDR), reset button works fine.

So I guess there might be a reset circuit issue within "m10_rgmii.v".

//PHY power-on reset control

parameter MSB = 20; // PHY interface: need minimum 10ms delay for POR

reg [MSB:0] epcount;

always @(posedge clk_50_max10 or negedge fpga_resetn)

if (!fpga_resetn)

epcount <= MSB + 1'b0;

else if (epcount[MSB] == 1'b0)

epcount <= epcount + 1;

else

epcount <= epcount;

assign phy_resetn = user_pb[0] & !epcount[MSB-1];

assign enet_resetn = phy_resetn;