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AShiv's avatar
AShiv
Icon for New Contributor rankNew Contributor
8 years ago

Nios II on the De0-Nano-SoC

I am wondering if it is possible to use just the Nios II and FPGA portion on this board, aka without HPS. So, that the Nios II doesn't need to use the HPS bridges to access the DDR3. I know it makes ...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
8 years ago

Hi,

DDR3 devices connected to the HPS and its signals are connected to the dedicated Hard Memory Controller

for HPS I/O banks.

Hence HPS is must required to access the DDR3.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)