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Altera_Forum
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15 years ago

Nios II Etherent Standard Design Example on 3C120 development kit

Hi All,

After trying multiple SOPC designs, several revisions of quartus/NIOS EDS, I have settled on the NiosII Ethernet example from the altera site

http://www.altera.com/support/examples/nios2/exm-net-std-de.html

The design is as simple as possible hardware wise. There are several issues in porting this to the 3C120 Dev Kit - (with help from others) I will try to list them here in this thread.

That the pin out used in the QAR file routes the Ethernet lines to the mezzanine connector rather then using the standard 881111 marvel phy on the baseboard. To use the baseboard phy I redefined the following pins in the pin planner

enet_resetn AD2

enet_txd0 W4

enet_txd1 AA5

enet_txd2 Y5

enet_txd3 W3

enet_rxd0 W8

enet_rxd1 AA6

enet_rxd2 W7

enet_rxd3 Y6

enet_tx_en AA7

enet_mdio L5

enet_mdc N8

enet_gtx_clk T8

enet_rx_dv AB4

enet_rx_clk B14

I also enabled RGMII mode in the software by adding the 881111 to the phy profile

alt_tse_system_info tse_mac_device[MAXNETS] = {

//Macro defined in altera_avalon_tse_system_info, should match TSE configuration

TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(

TSE_MAC, //tse_name

0, //offset

SGDMA_TX, //sgdma_tx_name

SGDMA_RX, //sgdma_rx_name

TSE_PHY_AUTO_ADDRESS, //phy_address

&marvell_cfg_rgmii, //phy_cfg_fp

DESCRIPTOR_MEMORY) //desc_mem_name

};

I added a 125 mhz enet phy pll generating 125, 25 and 2.5 mhz on it's 3 outputs. I added SOF files restraining the RGMII interfaces ala the linux design

The following is what I receive from the target

InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.

prep_tse_mac 0

Static IP Address is 169.254.1.234

prepped 1 interface, initializing...

[tse_mac_init]

INFO : TSE MAC 0 found at address 0x00000800

INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0]

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

WARNING : PHY[0.0] - Auto-Negotiation FAILED

MARVELL : Enabling auto crossover

MARVELL : PHY reset

INFO : PHY[0.0] - Checking link...

INFO : PHY[0.0] - Link not yet established, restart auto-negotiation...

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

WARNING : PHY[0.0] - Auto-Negotiation FAILED

WARNING : PHY[0.0] - Link could not established

WARNING : PHY[0.0] - Auto-Negotiation not completed! Speed = 100, Duplex = Full

TSEMAC SW reset bit never cleared!

OK, x=10002, CMD_CONFIG=0x00002000

MAC post-initialization: CMD_CONFIG=0x04000200

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

mctest init called

IP address of et1 : 169.254.1.234

Created "Inet main" task (Prio: 2)

Created "clock tick" task (Prio: 3)

Simple Socket Server starting up

[sss_task] Simple Socket Server listening on port 30

Simple Socket

Server

MAC:0007ED1180C9

IP ADDRESS:

169.254.1.234

TCP PORT:30

Telnet to me!!!!

Wondering if someone can tell me what I missed... The OS is obviously up... There is no phy link established...

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    As far as I can see you dont; if you'd rather work in a standard environment (ie emacs, + makefile) it should work fine - just not the path I took, as this company is a startup and has no "real" build environment/infrastructure (ie we use quartus for synthesis - nuff said?)

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Can someone tell me how I can extend the simple socket server design using the sopc builder?

    I've read here (http://www.altera.com/literature/hb/qts/qts_qii5v4.pdf) that the sopc builder creates a top level entity .v or .vhd file. So I made a change to the existing sopc system in the example (tserd_3c120) and re-generated it. This doesn't change anything in the the existing tserd_3c120.v file which is the top level entity for the quartus project. What am I missing here?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Typically you will make a top level file contain the sopc instance as well as your own logic tied to your own pinout. Say you add a UART interface: when you regenerate your sopc image you need to open your top, add the addtional signals from the large sopc generated file instance to the instantiation as well as add the pins to your top to route the new signals from sopc to the outside world

    sopc builder has no concept of what your pinout looks like or what your signal names are in your top level design.

    additionally as a debug tool, I have at some times placed PIO blocks in the hardware and tied status lines from various sopc generated modules to them to give the nios a place to check status on various signal states - this is done by hand in the top level...
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    ok, thanks! The example is in verilog which I'm not very fermiliar with (rather vhdl). I've added a PIO (1 pin wide) in the sopc system and then tried to change the tserd_3c120.v by declaring an input. I don't know how I can assign that input to an output such as the user_led[0]. ? I've tried a couple of things but error messages say that this input is not known to the sopc instance.

    For example: I want to take on clock pin which is my input and let it be shown on an led. I want to toggle that with a command via telnet. (I know about pin assignment editor and which pins I have to assign) What changes in my hardware design files in the example do I need to make?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    In your top file, add a counter to divide the clock down to a reasonable blink rate

    Ex: In many of my designs say I have a 50 mhz clk, I make a 29 bit counter that I route bit 26 to a led and use bit 29 to switch between it and a OS process that blinks the led via a PIO write - this shows me if 1 hardware is loaded (the counter blinking the LED slowly) and 2 the OS is running (the SW blinking it fast)

    To do this I add a wire from pio output .pio_out() in the SOPC builder's instance in the top to the io assign and switch with the ? operator

    assign led_output = counter[29] ? counter[26] : pio_out;

    reg [29:0] counter;

    always@(posedge clk_50mhz or negedge global_resetn)

    begin

    if(global_resetn == 0)

    begin

    counter <= 0;

    end

    else

    begin

    counter <= counter + 29'h00000001;

    end

    end
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Maybe my question is too simple. So if my clock input is called "ada_dco" and I've defined a ada_dco pio INPUT component in my sopc builer: how do I assign that component to the led? I would do it this way:

    module tserd_3c120

    ( ...

    input hsma_clk_in_p2,

    ...

    );

    assign user_led[0] = hsma_clk_in_p2;

    //hsma_clk_in_p2 is schamtic name for clock ada_dco

    //I still don't know how to use that pio sopc component in the verilog code.

    tserd_3c120_sopc tserd_3c120_sopc_inst

    ( ...

    .in_port_to_the_ada_dco (hsma_clk_in_p2), // <- ??

    ...

    );

    endmodule

    Before I implement a counter or anything I just want an led to output the clock signal on my telnet command (even if I don't see the blinking due to the frequency) and turn OFF on the telnet server command.