Nios II Etherent Standard Design Example on 3C120 development kit

In my reverse engineering and comparison between working and non working systems ... I find this hardware difference interesting. In the working version .. I find what would seem to be a very naughty verilog conditional clock swap statement:

assign tx_clk_to_the_tse_mac = (eth_mode_from_the_tse_mac) ? (enet_tx_125) : // GbE Mode = 125MHz clock

(ena_10_from_the_tse_mac) ? (enet_tx_2p5) : // 10Mb Mode = 2.5MHz clock

(enet_tx_25); // 100Mb Mode = 25MHz clock

whereas in the NON-WORKING hardware version I see they have tried to resynchronise all lcoks to 125MHz - sacrificing mark space ratios in the 25MHz and 2.5MHz clock domains as a result. I suspect that the 25MHz 3:2 Mark/Space that results from this.

From the 88E1111 Device Specification ... 4.12 RGMII/RTBI Interface Timing, (page217) - the Tcycle_high100 (High time for 100Base-T) is 16 -> 24nS.

2*8nS = 16nS ... thats right on the edge of the device specification with 2/5 : 3/5 mark space ratio. Dont think this is the problem ... but still think both solutions need work hardware wise.