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Honored ContributorNios II Etherent Standard Design Example on 3C120 development kit
Hi All,
After trying multiple SOPC designs, several revisions of quartus/NIOS EDS, I have settled on the NiosII Ethernet example from the altera site http://www.altera.com/support/examples/nios2/exm-net-std-de.html The design is as simple as possible hardware wise. There are several issues in porting this to the 3C120 Dev Kit - (with help from others) I will try to list them here in this thread. That the pin out used in the QAR file routes the Ethernet lines to the mezzanine connector rather then using the standard 881111 marvel phy on the baseboard. To use the baseboard phy I redefined the following pins in the pin planner enet_resetn AD2 enet_txd0 W4 enet_txd1 AA5 enet_txd2 Y5 enet_txd3 W3 enet_rxd0 W8 enet_rxd1 AA6 enet_rxd2 W7 enet_rxd3 Y6 enet_tx_en AA7 enet_mdio L5 enet_mdc N8 enet_gtx_clk T8 enet_rx_dv AB4 enet_rx_clk B14 I also enabled RGMII mode in the software by adding the 881111 to the phy profile alt_tse_system_info tse_mac_device[MAXNETS] = { //Macro defined in altera_avalon_tse_system_info, should match TSE configuration TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO( TSE_MAC, //tse_name 0, //offset SGDMA_TX, //sgdma_tx_name SGDMA_RX, //sgdma_rx_name TSE_PHY_AUTO_ADDRESS, //phy_address &marvell_cfg_rgmii, //phy_cfg_fp DESCRIPTOR_MEMORY) //desc_mem_name }; I added a 125 mhz enet phy pll generating 125, 25 and 2.5 mhz on it's 3 outputs. I added SOF files restraining the RGMII interfaces ala the linux design The following is what I receive from the target InterNiche Portable TCP/IP, v3.1 Copyright 1996-2008 by InterNiche Technologies. All rights reserved. prep_tse_mac 0 Static IP Address is 169.254.1.234 prepped 1 interface, initializing... [tse_mac_init] INFO : TSE MAC 0 found at address 0x00000800 INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... WARNING : PHY[0.0] - Auto-Negotiation FAILED MARVELL : Enabling auto crossover MARVELL : PHY reset INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link not yet established, restart auto-negotiation... INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... WARNING : PHY[0.0] - Auto-Negotiation FAILED WARNING : PHY[0.0] - Link could not established WARNING : PHY[0.0] - Auto-Negotiation not completed! Speed = 100, Duplex = Full TSEMAC SW reset bit never cleared! OK, x=10002, CMD_CONFIG=0x00002000 MAC post-initialization: CMD_CONFIG=0x04000200 [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created mctest init called IP address of et1 : 169.254.1.234 Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3) Simple Socket Server starting up [sss_task] Simple Socket Server listening on port 30 Simple Socket Server MAC:0007ED1180C9 IP ADDRESS: 169.254.1.234 TCP PORT:30 Telnet to me!!!! Wondering if someone can tell me what I missed... The OS is obviously up... There is no phy link established...16 Replies
Altera_ForumHi Crayner,
I have exactly the same problem and its driving me crazy ... did you work this out in the end? Any advice would be appreciated. Best Regards,- Altera_Forum
The only triple_speed_ethernet_design that works in this kit is from the Nios II software installation directory:-
C:\altera\91\nios2eds\examples\verilog\niosII_cycloneIII_3c120\triple_speed_ethernet_design Regarding the error "Error: Node instance "the_pll" instantiates undefined entity "altpllenet_pll” project". This is solved by reopening the SOPC Builder, and regenerating the SOPC system. After successful System generation, then recompile Quartus II project. The pll error will disappear. After that, to build and run SSS:- 1. Launch Nios II command shell. 2. Navigate to \triple_speed_ethernet_design\software_examples\app\simple_socket_server_tse_3c120_rgmiiand and run the script to compile the project by typing ./create-this-app as shown in create_this_app.jpg this creates the application but more importantly, patches the code to run on this devkit. i have tried just about every cut of code/hw/sw i found - this is the only way to get this baseline functional that i have found. 3. After successfully running the create-this-app script, you could import simple_socket_server_tse_3c120_rgmii and its corresponding bsp project (ucosii_net_tse_3c120_rgmii) to Nios II SBT for Eclipse to run the SSS. 4. To import, launch your Nios II SBT for Eclipse, from the "File" menu, choose "Import", under "Nios II Software Build Tools Project" >> choose "Import Nios II Software Build Tools Project" and click "Next". 5. Browse to the project path of where simple_socket_server_tse_3c120_rgmii locates and simply enter the desired project name. 6. Repeat the step (5) and (6) to import ucosii_net_tse_3c120_rgmii. 7. After importing both app and bsp projects to Nios II SBT for Eclipse, you are now ready to build and run the SSS project. - Altera_Forum
Crayner,
Thanks heaps for your help. It works! The only simple addition to your instruction set would be to advise to use the quartus project directory as the workspace you are importing into. Now to try to work out what hs been done so that I can utilise this on my target hardware design. Thanks again for taking the time to solve my problem! - Altera_Forum
good luck. This has been nothing but pain... ever see "Fight Club"?
- Altera_Forum
one of my favorite movies ... and yes... this was my first time in the "Altera Ethernet Interface", and I "had to fight!". Lets hope that I dont have to go to the same extremes to rid myself of the "Tyler Durdens" that will rise once I try to get this running on my actual target hardware :-)
- Altera_Forum
Thanks Crayner, everything compiled for me too (Quartus/Nios 10.0 and 3C120 bd). Though I would use the word "torture" instead of "pain" for describing the adventures with Altera's dev boards.
Now I'm looking forward to the wonderful adventures that await me as I attempt to customize the TSE example to stream A2D data to a PC. I'm sure the crystal-clear Altera TSE documentation will guide me along with ease. - Altera_Forum
In my reverse engineering and comparison between working and non working systems ... I find this hardware difference interesting. In the working version .. I find what would seem to be a very naughty verilog conditional clock swap statement:
assign tx_clk_to_the_tse_mac = (eth_mode_from_the_tse_mac) ? (enet_tx_125) : // GbE Mode = 125MHz clock (ena_10_from_the_tse_mac) ? (enet_tx_2p5) : // 10Mb Mode = 2.5MHz clock (enet_tx_25); // 100Mb Mode = 25MHz clock whereas in the NON-WORKING hardware version I see they have tried to resynchronise all lcoks to 125MHz - sacrificing mark space ratios in the 25MHz and 2.5MHz clock domains as a result. I suspect that the 25MHz 3:2 Mark/Space that results from this. From the 88E1111 Device Specification ... 4.12 RGMII/RTBI Interface Timing, (page217) - the Tcycle_high100 (High time for 100Base-T) is 16 -> 24nS. 2*8nS = 16nS ... thats right on the edge of the device specification with 2/5 : 3/5 mark space ratio. Dont think this is the problem ... but still think both solutions need work hardware wise. - Altera_Forum
is the marvell phy 88e1111 programmable through software?
- Altera_Forum
so, it guesses what you want it to do and just does it.
...any issues with lead paint in your home town? - Altera_Forum
is there any specific documentation on that example simple_socket_server_tse_3c120_rgmii ? I've searched on a whole lot of TSE and NIOS II manuals.
The example is working as far as toggling the LED's goes. But the "S" - Lightshowcommand isn't working. Is that supposed to make the LED's blink? @crayner: why do you need to import the ucosii_net_tse_3c120_rgmii into the Nios II SBT ?
