Nios II and Cyclone II confusion

this forum is ment to be a place for asking questions and help each other, so keep on asking :-)

with a fpga you are free to do things very easily and fast. if you need a "task" to be done very fast, implement it in hardware (HDL) you can split jobs where some parts are pure software and others are hardware executed.

one example is the often used crc function. imagine a crc done purely in software and yopu need to calculate the crc over 1 MByte. that would take a lot of clock cycles. imagine this job done as pure hardware that is trimmed only for that but does this very fast. now your c/c++ application is coded around your hardware crc. you can create your own crc hw accelerated function as a ip block where you have the crc register and the data register. but nios also enables you to create custum instructions where your crc is calculated with only one clock cycle per data

you could implement a fft functionality in hardware and let your c/c++ application fetch input data from ethernet, and send the fft out data back via ethernet.

if you think about video processing, store frames with you c/c++ application and let the image processing be done by a custom hardware function where this ip does the image data fetch automatically sent the data from processing block to processing block and at the end store it to the desitination memory.

hope you get the idea of mixing hardware and software