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Altera_Forum
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17 years ago

Nios II and ADC -- Cyclone III Dev. Board

Sorry, I've only just started using Altera FPGAs, and so far things went fine with Verilog and without using Nios II. I would now like to use a Nios II soft-processor for some signal processin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I would like to sample at 100-150MHz @ 14bits, so sampling through the Nios does not seem like an option. I might need DMA for high speed.

I'm still confused about SOPC Builder, how to bring parts together. And I'm also confused how to connect the ADC with the SDRAM... Verilog or with Block Diagrams should be possible.

Thanks for any help!