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Altera_Forum
Honored Contributor
Honored ContributorNios II and ADC -- Cyclone III Dev. Board
Sorry, I've only just started using Altera FPGAs, and so far things went fine with Verilog and without using Nios II. I would now like to use a Nios II soft-processor for some signal processin...
Altera_ForumHonored Contributor
Honored ContributorI want to make sure I understand the problem correctly.
You have samples and you need to write these samples into SDRAM using Verilog not the NIOS. I know that NIOS can write into SDRAM. So, you can pass these signals from Quartus to NIOS using SOPC. Then NIOS can do the writing for you. However, NIOS reading rate is slow and varying. So, the sampling accuracy will be bad. So, I recomend to sample and write into SDRAM using Verilog Quartus. Then NIOS can read from SDRAM to do your signal processing. The question now is how Verilog do the wrting into SDRAM??? Actually, I still search about it. So, lets work in this issue together. OK
