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Altera_Forum
Honored Contributor
16 years agoDaixiwen,
Thanks for your suggestion. I'll try it. I'm not using a PLL. Since the system is very simple, just including a cpu, an on-chip memory, a JTAG UART and a system clock timer, I just use the 100 MHz external clock to drive all the components. The reset signal is set to Vcc. Actually I just assigned one pin, the clock. Every time I tried to download the sof file to the FPGA, there was a message saying "expect 1 device, but detect 2. Operation failed". I could only press the auto-detect button, and then 2 devices showed up, a MAX II CPLD and a stratix ii gx fpga. Then I downloaded the sof file to the fpga with no error. I'm not sure if this is a problem. Thanks, Xiaorong