Need help running the PCIe to DDR3 SDRAM reference design

I suspect you're using Quartus 9.1? The timing analysis methodology for external memories changed in 9.1. To update the design, open the DDR3 IP in the mega wizard and regenerate it. Then run Analysis and Synthesis. Then run the <>_pin_assignments.tcl. I also disabled the D6 delay assignment on mem_clk as I wasnt sure why this would be required, probably something to do with early timing models or ES silicon. Then do a full compile.

I just did this and it passes timing with the exception of one signal, coreclkout, looking in TQ I think this failure is a false path.

I doubt the PC application is pulling data from the PCs harddrive, most apps like these just generate incremental or pseudo random data.

AN431 has some info on the throughput. In this project the DDR3's BW is far greater than the PCIe, so i suspect the throughput is limited to the PCIe chipset and FPGA transceiver channels.