Need controller Timing parameters of Cyclone V memory device

Hi Team,

Greetings..!

I am performing the Signal Integrity analysis of Cyclone V (5CSXFC6D6F31C6N) and DDR Interface (DDR3, 800MHz).

Kindly help us in deriving the min and Max values of the Following parameters to complete the analysis.

1. tCKAC - Addr/Cmd prelaunch delay, relative to CK(r) (1T)

2. tCKCTL - ctl prelaunch delay, relative to CK(r)

3. tCKDQS - DQS delay, relative to CK

4. tDQSDQ - DQ prelaunch delay, relative to DQS

5. tDQDQS - Max. tolerable DQ to DQS skew (-,+) (derived from tDS, tDH)

6. tDS - DQ valid to shifted DQS

7. tDH - Shifted DQS to DQ invalid.

looking forward for your response.

Regards,

Prasad Aginiparthi.