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MarkZop
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3 years ago

Multiple .vqm files have module with the same name, which is causing an error.

Hello,

I currently am building a design that has multiple .vqm files. When I attempt to synthesize the top level, I receive an error that is ultimately due to 2 .vqms having a module with the same name. As a workaround, I can set the syn_netlist_hierarchy attribute to '1', to flatten the netlist, resulting in unique names, but ideally I'd like to maintain the hierarchy. Is there a better solution? Is there a way I can explicitly define a module's netlist name such that I can ensure they are unique?

This is ultimately what I'm seeing.

Verilog HDL warning at vqm_file_a.vqm(319302): overwriting previous definition of fifo_gen_async_0 module File:

Verilog HDL info at vqm_file_b.vqm(9156): previous definition of module fifo_gen_async_0 is here File:

Verilog HDL error at vqm_file_b.vqm(2391): can't find port "rx_fifo_read_count_0"

Thanks!

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