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OlegT's avatar
OlegT
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

MSI with avalonMM-DMA ip

Hello. I use pcie HIP with avalon-mm-dma interface, as an endpoint. Cyclone10GX evaluation kit. I need to send custom MSI to root complex (ubuntu PC). rxm_irq signals are not available due to mm-d...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    4 years ago

    Hi,


    I could not find the part that you have mentioned in the document. May I know which document you are referring to?


    According to the PCI Local Bus Specification 2.3,

    "If the Multiple Message Enable field (bits 6-4 of the Message Control register) is non-zero, the device is permitted to modify the low order bits of the message data to generate multiple messages."


    Thanks

    Best regards,

    KhaiY




KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY