New Contributor
Regular ContributorHi,
To enable MSI,
1. Set MSI Enable of MSI Control register, this bit is mapped to bit[16] of offset 0x50 in configuration space register.
2. Set Interrupt Disable bit[10] of Command register at configuration space offset register 0x4 to disable legacy interrupt.
3. Set bit[1] (Memory space) and bit[2] (Bus Master) of Command Register at configuration space offset register 0x4 to enable the ability to generate MSI message.
Once users trigger the rxm_irq, the PCIe core will generates the interrupt message.
You may refer to Figure 4–13 for IP Compiler for PCI Express Avalon-MM Interrupt Propagation to the PCI Express Link
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf
You may also refer to the below link for PCIe Interrupt Handling but the design is for Stratix V.
https://community.intel.com/t5/FPGA-Wiki/Handling-PCIe-Interrupts/ta-p/736044
https://community.intel.com/t5/FPGA-Wiki/Handling-PCIe-Interrupts/ta-p/736044
Thanks
Best regards,
KhaiY
New ContributorHello KhaiY,
I have ensured that I have correctly performed steps 1-3 on the host. I am also driving high the rxm_irq within the FPGA's design. When I driver rxm_irq high then read the Interrupt Status Register using the CRA slave port at address 0x0040, I see the corresponding bit set. However, I don't see an MSI message going upstream. I still have the following questions:
1. How long should I drive the rxm_irq high in order to see an MSI sent upstream?
2. How is acknowledgement of the interrupt supposed to work since I'm not supposed to be writing to the CRA port from within my logic as the documentation claims it's "reserved for Root Complexes".
I see a lot of info for implementing MSI-x in the projects you referred me to, but not a lot regarding setting up MSI interrupts. Are there example projects that will answer these questions for me? I'm sure I'm missing something.
Many thanks for your responses and willingness to help.
Daryl
