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dfowlkes's avatar
dfowlkes
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4 years ago

MSI PCIE Interrupt set up using Avalon-MM PCIe Hard IP Core as a Qsys component...

I'm confused about how to properly set up MSI interrupts across the PCIe interface using the Avalom-MM interface of the PCie Hard IP Core. I am confident the PCIe host driver is enabling MSI's corre...
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    dfowlkes
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    4 years ago

    Thanks KhaiY. All I have to work with is the Stratix IV board. I guess my real question relates to how an endpoint should invoke MSIs for the PCIe core that's compatible with that board via the Avalon-MM interface. Do I use the physical RxmIrq<> lines and have the core generate the MemWr TLP upstream or should I use the msiintfc<> bus info and make use of the Txs slave interface? I've tried the RxmIrq approach and saw the correct bit set in the CRA Interrupt Status Register (0x0040), but the root complex did not call the ISR of my host driver.

    Daryl