Forum Discussion
Jayasurya
New Contributor
2 years agoHi Aikeu,
Thanks for the reply.
We have changed the level translator, ESD diode part number compared to the reference design.
I have done the changes in the device tree file(arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi). In my custom board DDR size has changed from 8GB to 4GB. I have attached the dts file for your reference.
I have loaded the .jic file in the QSPI, so that FSBL will load from QSPI and I am trying to boot from MMC(SD Card).
Best Regards,
Jayasurya R.
Jayasurya
New Contributor
2 years agoHi Aikeu,
Sorry, my dtsi file didn't get added last time.
Thanks,
Jayasurya R.