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PSriv8's avatar
PSriv8
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5 years ago

May I use WYSIWYG for hardware or is it applicable only for synthesis?

May I use WYSIWYG for hardware or is it applicable only for synthesis? I am trying to calculate the delay of a barrel shifter using the DE-115 FPGA board and digital oscilloscope. The shifter input...
sstrell's avatar
sstrell
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5 years ago

It is available in Lite and Standard editions, but like you say, it is only for when the results of a 3rd-party synthesis tool are brought into Quartus for place and route.

You could make use of timing reports in the Timing Analyzer to see the calculated delay from an input to an output.

#iwork4intel

PSriv8's avatar
PSriv8
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5 years ago
Thank you for your reply. I still have few questions in mind, it might be very basic as I m still learning:
1. I didn't quite understand the meaning of using a 3rd party synthesis tool, coz as per my knowledge we have to use a third-party tool for synthesis (from cadence or synopsis etc) in order to calculate power, area and delay of a circuit. Does quartus have a synthesis tool for calculating the parameters like other synthesis tools can do?

2. I have designed a block diagram file (.bdf) with three stages of 2x1 muxes connected in series i.e. Output of stage 1 connected to input of stage 2 and output of stage 2 is connected to input of stage 3. The inputs are connected to switched of FPGA board and outputs are connected to LEDs. Now I connect the input switches and LEDs to a Digital oscilloscope and capture the waveform. The output changes after a delay of almost 12ns after it detects change in input.

I was expecting that taking output from various stages would require different time, for example: if tapping input from stage 1 and output from stage 1 requires time T, then tapping input from stage 1 and output from stage 2 should be 2T to and tapping input from stage 1 and output from stage 3 should be 3T. However, I am getting a delay of 12ns everytime irrespective of no of stages used. That is why I wanted to use the WYSIWYG feature. Could you please suggest.
  • sstrell's avatar
    sstrell
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    5 years ago

    1) All the features you mentioned are built into Quartus. Using a 3rd party synthesis tool is optional, and usually dictated by the company you work for I have found. Built-in synthesis is usually more than sufficient for most designers and it's one less tool you have to learn/use/manage.

    2) As mentioned, design optimization is probably causing this. If you need specific delays for a design, you need to incorporate them into SDC timing constraints, such as set_max_delay and set_min_delay. If you're not familiar with timing constraints and analysis, start here with this training:

    https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

    #iwork4intel

    • PSriv8's avatar
      PSriv8
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      5 years ago

      Thank you for your reply. I will explore the Quartus Synthesis feature to synthesize my design.

      Regarding the SDC constraints, I have gone through the link you have shared and completed all the timing constraint sessions, which is very helpful. Thank you for sharing it.

      1. However, I am not sure whether setting these timing constraints will provide me the actual delay required from input to output. We need to speculate the timing of various digital elements in advance to write the timing constraint, but I want to calculate the actual time required by the output (LED) to change its state once the input (Switch) is flipped. The design optimization is not letting me calculate the actual time on the FPGA board using DSO. Therefore I am trying to find out whether there is any feature available that could preserve the circuit as it is so that I can calculate the actual delay. I found the 'Preserve Registers' option as well, but I don't find it useful for preserving the delay of the circuit.

      2. As you have mentioned that Quartus already have a synthesis tool, can we calculate the processing time of a digital element such as gates/multiplexers/flip-flops, etc? For example,

      • In 65 nm technology, delay of a 2x1 mux = 50 ps (Measured using Cadence)

      Can we calculate it using Quartus as well?

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        5 years ago

        In the Timing Analyzer, you could generate a path report from an input to an output to see all the delays along the path. Is that what you want?

        #iwork4intel