May I not supply voltage to VCCIO during power up and configuration? 

Hi.

Internal weak pull-up resistors interfere with my scheme. As far as I know the pull-up resistors cannot be disconnected during power up and configuration. May I not supply voltage to VCCIO?

​​​​​​​How long may I not supply voltage to VCCIO? I configure FPGA using my computer.

Best regards,

dinam