Forum Discussion
Occasional ContributorMAXII CPLD VGA CONTROLLER QUESTIONS
Hi ,
Good try for your project.
Question 1
The behavior you're seeing can be expected when dealing with precise timing in video signal processing. To address this, consider extending the horizontal active region slightly, adding timing margins, and thoroughly testing your design. This will help ensure that all pixels are displayed correctly without glitches.
Question 2
I never try the same implementation in MaxII before, but I can lay down some of tips for you to move forward.
Using two single-port SRAMs in a ping-pong buffering scheme is a practical approach to achieve the effect of dual-port memory, especially in video processing applications where simultaneous read and write operations are necessary. Here’s a detailed explanation of how to manage ping-pong buffering between two single-port SRAMs.The basic concept involves using two SRAMs alternately: while one SRAM is being written to, the other is being read from. This alternation is controlled by a synchronization signal such as VSYNC or a video enable signal. The VSYNC or video enable signal will be used to switch between the two SRAMs, typically at the end of each frame or a predefined interval. Additionally, control logic is required to manage the read and write operations to the SRAMs.
To implement ping-pong buffering, you start by initializing the buffers. Set Buffer A as the initial write buffer and Buffer B as the initial read buffer. During the operation, while writing to Buffer A, you read from Buffer B, and vice versa. When the VSYNC or video enable signal is triggered, the roles of the buffers are switched: Buffer A becomes the read buffer, and Buffer B becomes the write buffet
Other related information about MaxII you may refer to
Hope that able to help you move forward.
Regards,
Wincent
Regular ContributorHi ,
Good try for your project.
Question 1
The behavior you're seeing can be expected when dealing with precise timing in video signal processing. To address this, consider extending the horizontal active region slightly, adding timing margins, and thoroughly testing your design. This will help ensure that all pixels are displayed correctly without glitches.
Question 2
I never try the same implementation in MaxII before, but I can lay down some of tips for you to move forward.
Using two single-port SRAMs in a ping-pong buffering scheme is a practical approach to achieve the effect of dual-port memory, especially in video processing applications where simultaneous read and write operations are necessary. Here’s a detailed explanation of how to manage ping-pong buffering between two single-port SRAMs.The basic concept involves using two SRAMs alternately: while one SRAM is being written to, the other is being read from. This alternation is controlled by a synchronization signal such as VSYNC or a video enable signal. The VSYNC or video enable signal will be used to switch between the two SRAMs, typically at the end of each frame or a predefined interval. Additionally, control logic is required to manage the read and write operations to the SRAMs.
To implement ping-pong buffering, you start by initializing the buffers. Set Buffer A as the initial write buffer and Buffer B as the initial read buffer. During the operation, while writing to Buffer A, you read from Buffer B, and vice versa. When the VSYNC or video enable signal is triggered, the roles of the buffers are switched: Buffer A becomes the read buffer, and Buffer B becomes the write buffet
Other related information about MaxII you may refer to
Hope that able to help you move forward.
Regards,
Wincent
Armando1989Hi Wincent!
Thanks for your kind reply
- Yep, if i notice any issue on monitors, i would contract just a little porch region so extend video enable region. So far seems this one is working ok with current setup.
- For sram thing... im not sure if is worth using some 4 latches between data/address bus on cpu/cpld and flip output enable based on wheter is reading or writing memory based ie: on vsync.... or Using 2 address and 2 data busses and alternate reading between them on cpld again based on vsync, the actual write address bus being used by cpu set cpld as high z while reading the other with cpld... Major pain for me is this multiplexing stuff.
I guess i would go first for expensive solution double port sram :D, im little worried about bus conflict issues to be honest.
BR
- Armando1989Hi Wincent!Added one more module to multiplex between SRAMS, i guess is something as you suggested... if not, let me knowThanks in advance!module memory_mux #(parameter ADDRESS_BUS_WIDE,parameter DATA_BUS_WIDE)(input clk,input reset,input wire vsync,input wire[ADDRESS_BUS_WIDE-1:0]INTERNAL_ADDRESS_BUS,input wire[DATA_BUS_WIDE-1:0]MEMORY_A_DATA_BUS,input wire[DATA_BUS_WIDE-1:0]MEMORY_B_DATA_BUS,output wire[DATA_BUS_WIDE-1:0]INTERNAL_DATA_BUS,output wire[ADDRESS_BUS_WIDE-1:0]MEMORY_A_ADDRESS_BUS,output wire[ADDRESS_BUS_WIDE-1:0]MEMORY_B_ADDRESS_BUS);reg swap; //SWITCH CONTROLalways @(negedge vsync)begin //VSYNC FALLING EDGE WILL DIRECT CHANGE S-RAMif(reset)beginswap<=0; //INITIALLY CPLD WILL READ SRAM-A AND CPU WILL WRITE SRAM-Bendelseswap<=~swap;endassign MEMORY_B_ADDRESS_BUS=!swap?15'bzzzzzzzzzzzzzzz:INTERNAL_ADDRESS_BUS; //CPLD DRIVES SRAM-A ADDRESS BUS, CPLD FLOATS SRAM-B ADDRESS BUSassign MEMORY_A_ADDRESS_BUS=swap?15'bzzzzzzzzzzzzzzz:INTERNAL_ADDRESS_BUS; //CPLD DRIVES SRAM-B ADDRESS BUS, CPLD FLOATS SRAM-A ADDRESS BUSassign INTERNAL_DATA_BUS=swap?MEMORY_B_DATA_BUS:MEMORY_A_DATA_BUS; //SWITCH BETWEEN DATA PORTSendmoduleSo result is ping-pon both address buses:
Processor must know at init it should direct SRAM-B and float SRAM-A port, just the oposite cpld.... I set positive vsync as aux signal for cpu. With all of this thw whole 100 pins are used on max2 device.
Just tested with ports connected apears fine... Next would be construction of pcb and interface with some uc such as smt32...
BR
