Occasional ContributorMAXII CPLD VGA CONTROLLER QUESTIONS
Hi there!
Im doing some experiment with vga under epm570t100 for 640x480 vga controller, apparently all is quite functional per results on vga screen, however i would like any comments from your expert experience... :D. Design and simulation files attached for your reference or use.
My first approach is interfacing controller with 16kx32 sram and shift each 16 bits in memory as individual pixels (black or white).
1-When interface either 16/8bit data bus i find horizontal frame barely can fit the bits(pixels), on my design, last shifted pixel at the rising edge of 25MHz clock_enable signal is just at the end of horixontal line, it is on the falling edge of the video active region... almost a glitch
Per screen results when playing with first/last pixel with external switch on data bus, it appears to eat those pixels well... (3 pixels on 1920 screen resolution equivalent to 1 pixel on 640):
Is this behavior to be expected?, maybe some designs extend a little the horizontal active region to fit pixels?
2-I find 2 port srams quite attractive for this application, since can write and read independently, u can see here an example of 16bits x32k one.
The question is... if two cheaper one port sram is to be used, have u any experience how to manage ping-pong buffering between 2 single port stams like this one?
Ie: using vsync or video enable signal to command a switch between 2 rams, one being filled the other being read.... Have u any experience on this one?
Thanks in advance!
Some extra photos for fun :D:
All 16bits "on"
3/4 bits off
all off
alternated
Board
Hi ,
Good try for your project.
Question 1
The behavior you're seeing can be expected when dealing with precise timing in video signal processing. To address this, consider extending the horizontal active region slightly, adding timing margins, and thoroughly testing your design. This will help ensure that all pixels are displayed correctly without glitches.
Question 2
I never try the same implementation in MaxII before, but I can lay down some of tips for you to move forward.
Using two single-port SRAMs in a ping-pong buffering scheme is a practical approach to achieve the effect of dual-port memory, especially in video processing applications where simultaneous read and write operations are necessary. Here’s a detailed explanation of how to manage ping-pong buffering between two single-port SRAMs.The basic concept involves using two SRAMs alternately: while one SRAM is being written to, the other is being read from. This alternation is controlled by a synchronization signal such as VSYNC or a video enable signal. The VSYNC or video enable signal will be used to switch between the two SRAMs, typically at the end of each frame or a predefined interval. Additionally, control logic is required to manage the read and write operations to the SRAMs.
To implement ping-pong buffering, you start by initializing the buffers. Set Buffer A as the initial write buffer and Buffer B as the initial read buffer. During the operation, while writing to Buffer A, you read from Buffer B, and vice versa. When the VSYNC or video enable signal is triggered, the roles of the buffers are switched: Buffer A becomes the read buffer, and Buffer B becomes the write buffet
Other related information about MaxII you may refer to
Hope that able to help you move forward.
Regards,
Wincent
