Occasional ContributorMAXII CPLD VGA CONTROLLER QUESTIONS
Hi ,
Good try for your project.
Question 1
The behavior you're seeing can be expected when dealing with precise timing in video signal processing. To address this, consider extending the horizontal active region slightly, adding timing margins, and thoroughly testing your design. This will help ensure that all pixels are displayed correctly without glitches.
Question 2
I never try the same implementation in MaxII before, but I can lay down some of tips for you to move forward.
Using two single-port SRAMs in a ping-pong buffering scheme is a practical approach to achieve the effect of dual-port memory, especially in video processing applications where simultaneous read and write operations are necessary. Here’s a detailed explanation of how to manage ping-pong buffering between two single-port SRAMs.The basic concept involves using two SRAMs alternately: while one SRAM is being written to, the other is being read from. This alternation is controlled by a synchronization signal such as VSYNC or a video enable signal. The VSYNC or video enable signal will be used to switch between the two SRAMs, typically at the end of each frame or a predefined interval. Additionally, control logic is required to manage the read and write operations to the SRAMs.
To implement ping-pong buffering, you start by initializing the buffers. Set Buffer A as the initial write buffer and Buffer B as the initial read buffer. During the operation, while writing to Buffer A, you read from Buffer B, and vice versa. When the VSYNC or video enable signal is triggered, the roles of the buffers are switched: Buffer A becomes the read buffer, and Buffer B becomes the write buffet
Other related information about MaxII you may refer to
Hope that able to help you move forward.
Regards,
Wincent
