MAXII CPLD ADDRESS GENERATION GLITCHES

Thanks,
I overlooked clk definition in .sdc file which is basically o.k. and should be sufficient to report timing violations in internal logic. Reported Fmax is about 140 MHz, suggesting much of timing margin. I don't see how the glitches can be brought up in address counter and mux logic. I rather guess it's an logic analyzer artifact due to insufficient ground connection or unsuitable level threshold setting. I presume that address lines are not externally driven during glitch period.