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Armando1989's avatar
Armando1989
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

MAXII CPLD ADDRESS GENERATION GLITCHES

Hi There Im working on VGA module with EPM240T100C4, all seems fine except adress bus outputs. Im facing glitches, which not present on questaSim gate analisys but are present on logic analy...
Fpga Devkit
  • FvM's avatar
    FvM
    1 year ago

    Thanks,
    I overlooked clk definition in .sdc file which is basically o.k. and should be sufficient to report timing violations in internal logic. Reported Fmax is about 140 MHz, suggesting much of timing margin. I don't see how the glitches can be brought up in address counter and mux logic. I rather guess it's an logic analyzer artifact due to insufficient ground connection or unsuitable level threshold setting. I presume that address lines are not externally driven during glitch period.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,
"glitches" during floating address lines are just expectable because logic level is undefined.

I already mentioned that using vsync_rec as clock is bad design practice.

Better use synchronous edge detection

always @(posedge clk)begin
vsync_reg<=vsync;
vsync_reg1 <= vsync_reg;
if (!vsync_reg & vsync_reg1)
swap <= !swap;
end

Armando1989's avatar
Armando1989
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi FvM

Yes, ive already solved by retiming vsync, however i applied your solution better so no clk domain cross, problem is solved, no further artifacts nor glitches:

Just one more "notation question", could below statement be modified so it updates when bus wide changes instead of manually add by hand according to bus wide changes?. Im not quite concern on this regard indeed...

Thanks so much for your help!