Forum Discussion
Occasional ContributorMAXII CPLD ADDRESS GENERATION GLITCHES
Thanks,
I overlooked clk definition in .sdc file which is basically o.k. and should be sufficient to report timing violations in internal logic. Reported Fmax is about 140 MHz, suggesting much of timing margin. I don't see how the glitches can be brought up in address counter and mux logic. I rather guess it's an logic analyzer artifact due to insufficient ground connection or unsuitable level threshold setting. I presume that address lines are not externally driven during glitch period.
Super ContributorHi,
"glitches" during floating address lines are just expectable because logic level is undefined.
I already mentioned that using vsync_rec as clock is bad design practice.
Better use synchronous edge detection
always @(posedge clk)begin
vsync_reg<=vsync;
vsync_reg1 <= vsync_reg;
if (!vsync_reg & vsync_reg1)
swap <= !swap;
end
Occasional ContributorHi FvM
Yes, ive already solved by retiming vsync, however i applied your solution better so no clk domain cross, problem is solved, no further artifacts nor glitches:
Just one more "notation question", could below statement be modified so it updates when bus wide changes instead of manually add by hand according to bus wide changes?. Im not quite concern on this regard indeed...
Thanks so much for your help!
