Forum Discussion
Max Tpd of a LUT -> calculation of a maximum number of the LUTs allowed between two flops.
Hello,
I'd like to create a thumb rule about how many LUTs I would allow between two flops when I synthesize a module as a stand alone module.
I thought about a thumb rule of giving 50% of the timing budget to logic elements and 50% for route.
In order to know how many logic elements (LUTs) I would allow between two flops, I need to know a Tpd of a LUT (worst path).
So, the formula should be simple:
Max # of LUTs between flops = (1/Freq) * 0.5 / (Tpd of LUT)
So, anyway, where can I see the timing parameters of the LUT and other logic elements in the device?
Hi,
May I know which device you are using for your design? This is because different device have different architecture. You may find the device handbook, for an example Arria 10 Handbook with link below:
Thanks.
5 Replies
- MEIYAN_L_Intel
Frequent Contributor
Hi,
You can use the timing analyzer tool to see the timing parameter.
You may refer to the reference document as links below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_tq_tutorial.pdf
https://www.youtube.com/watch?v=_7mMYhuQIbY
Thanks
- ldm_as
Occasional Contributor
Thanks, but is there a doc, which describes the available LUTs in the devices with the LUT structure?
- MEIYAN_L_Intel
Frequent Contributor
Hi,
May I know which device you are using for your design? This is because different device have different architecture. You may find the device handbook, for an example Arria 10 Handbook with link below:
Thanks.
- ldm_as
Occasional Contributor
I use Arria-10 GX-1150 (the same device as on EVB)
- MEIYAN_L_Intel
Frequent Contributor
Hi,
You can refer to the Arria 10 Handbook:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf
Thanks.