Forum Discussion
ldm_as
Occasional Contributor
Occasional ContributorMax Tpd of a LUT -> calculation of a maximum number of the LUTs allowed between two flops.
Hello, I'd like to create a thumb rule about how many LUTs I would allow between two flops when I synthesize a module as a stand alone module. I thought about a thumb rule of giving 50% of the timi...
Hi,
May I know which device you are using for your design? This is because different device have different architecture. You may find the device handbook, for an example Arria 10 Handbook with link below:
Thanks.
MEIYAN_L_Intel
Frequent Contributor
Frequent ContributorHi,
You can use the timing analyzer tool to see the timing parameter.
You may refer to the reference document as links below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_tq_tutorial.pdf
https://www.youtube.com/watch?v=_7mMYhuQIbY
Thanks
ldm_asThanks, but is there a doc, which describes the available LUTs in the devices with the LUT structure?
