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RVanD5's avatar
RVanD5
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3 months ago
Solved

LVDS_TX error on too many fanout, but connected to single pin - C10LP

I have a very simple project where we migrate a Arria 10 NCO design to a

Cyclone 10 LP. We regenerated the LVDS IP as this is different on the C10LP.

But we get this error:

Error (15885): Output port "DATAOUT" of DDIO_OUT WYSIWYG "dac_lvds:dac_lvds_inst|altlvds_tx:ALTLVDS_TX_component|dac_lvds_lvds_tx:auto_generated|dac_lvds_ddio_out1:outclock_ddio|ddio_outa_0" has too many fan-outs.

Looking at the top level VHDL, we see no reason of any of the DDIO IP block to be

connected to multitple output pins. So there error makes not much sense, and no

clue where to continue this search. Using Q24.1Std under Linux.

Thanks in advance for your time.

Kind regards, Rob

  • FvM's avatar
    FvM
    3 months ago

    Hi,
    the error is caused by ALTLVDS_TX tx_outclock connection. You are using it to drive NCO IP in your design. Honestly I don't understand why, that doesn't seem to make sense because tx_outclock is intended only as a reference for LVDS output signals. Fortunately we don't need to understand the design objective to fix the error.

    Problem is that tx_outclock is the output of a DDIO_OUT block rather than a direct PLL clock that can be used internally. If you want access to LVDS_TX fast_clock PLL signal, you need to switch to ALTLVDS_TX external PLL option. Or generate 300 MHz clock with other PLL.

    Regards
    Frank

4 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 months ago

    Hi,
    the error is caused by ALTLVDS_TX tx_outclock connection. You are using it to drive NCO IP in your design. Honestly I don't understand why, that doesn't seem to make sense because tx_outclock is intended only as a reference for LVDS output signals. Fortunately we don't need to understand the design objective to fix the error.

    Problem is that tx_outclock is the output of a DDIO_OUT block rather than a direct PLL clock that can be used internally. If you want access to LVDS_TX fast_clock PLL signal, you need to switch to ALTLVDS_TX external PLL option. Or generate 300 MHz clock with other PLL.

    Regards
    Frank

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 months ago

    Hi,
    I see why you are using 300 MHz clock for NCO. As stated, the NCO and related logic must be driven directly by a 300 MHz PLL clock. Original Arria 10 design works possibly different in this regard, driving tx_outclock by a PLL output rather than DDIO_OUT.

    NCO in Cyclone 10 LP speedgrade 7 causes timing violations at 300 MHz, you need fastest speedgrade 6.

    Regards
    Frank

  • RVanD5's avatar
    RVanD5
    Icon for New Contributor rankNew Contributor
    3 months ago

    Hi Frank,

    Many thanks! Indeed, the use of tx_outclock was the cause of the error. In the Arria 10, we could use the 'pll_extra_clock' to generate the 300 MHz clock, but unfortunately, the C10LP does not have this option. We use the 300 MHz to clock the NCO, as this is the outgoing samplerate (DDR I/Q over a 16-bit bus, so 600 MHz LVDS rate).

    Speed grade -6 is only for commercial devices, c10lp-51002-683251-666518.pdf, correct? We need the -40 deg temp specification (at least -25 deg). So, I am drawing the conclusion that the C10LP for this purpose is no-go?

    Thanks, Rob

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 months ago

    Hi Rob,
    you are right, no Cyclone 10 LP I6 speed grade available, unfortunately. Go for Agilex 3?

    Best regards
    Frank