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New ContributorLVDS_TX error on too many fanout, but connected to single pin - C10LP
Hi,
the error is caused by ALTLVDS_TX tx_outclock connection. You are using it to drive NCO IP in your design. Honestly I don't understand why, that doesn't seem to make sense because tx_outclock is intended only as a reference for LVDS output signals. Fortunately we don't need to understand the design objective to fix the error.
Problem is that tx_outclock is the output of a DDIO_OUT block rather than a direct PLL clock that can be used internally. If you want access to LVDS_TX fast_clock PLL signal, you need to switch to ALTLVDS_TX external PLL option. Or generate 300 MHz clock with other PLL.
Regards
Frank
New ContributorHi Frank,
Many thanks! Indeed, the use of tx_outclock was the cause of the error. In the Arria 10, we could use the 'pll_extra_clock' to generate the 300 MHz clock, but unfortunately, the C10LP does not have this option. We use the 300 MHz to clock the NCO, as this is the outgoing samplerate (DDR I/Q over a 16-bit bus, so 600 MHz LVDS rate).
Speed grade -6 is only for commercial devices, c10lp-51002-683251-666518.pdf, correct? We need the -40 deg temp specification (at least -25 deg). So, I am drawing the conclusion that the C10LP for this purpose is no-go?
Thanks, Rob
