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New ContributorLVDS_TX error on too many fanout, but connected to single pin - C10LP
Hi,
the error is caused by ALTLVDS_TX tx_outclock connection. You are using it to drive NCO IP in your design. Honestly I don't understand why, that doesn't seem to make sense because tx_outclock is intended only as a reference for LVDS output signals. Fortunately we don't need to understand the design objective to fix the error.
Problem is that tx_outclock is the output of a DDIO_OUT block rather than a direct PLL clock that can be used internally. If you want access to LVDS_TX fast_clock PLL signal, you need to switch to ALTLVDS_TX external PLL option. Or generate 300 MHz clock with other PLL.
Regards
Frank
Super ContributorHi,
I see why you are using 300 MHz clock for NCO. As stated, the NCO and related logic must be driven directly by a 300 MHz PLL clock. Original Arria 10 design works possibly different in this regard, driving tx_outclock by a PLL output rather than DDIO_OUT.
NCO in Cyclone 10 LP speedgrade 7 causes timing violations at 300 MHz, you need fastest speedgrade 6.
Regards
Frank
