Forum Discussion
RVanD5
New Contributor
11 months agoLVDS_TX error on too many fanout, but connected to single pin - C10LP
I have a very simple project where we migrate a Arria 10 NCO design to a Cyclone 10 LP. We regenerated the LVDS IP as this is different on the C10LP. But we get this error: Error (15885): Output ...
- 11 months ago
Hi,
the error is caused by ALTLVDS_TX tx_outclock connection. You are using it to drive NCO IP in your design. Honestly I don't understand why, that doesn't seem to make sense because tx_outclock is intended only as a reference for LVDS output signals. Fortunately we don't need to understand the design objective to fix the error.
Problem is that tx_outclock is the output of a DDIO_OUT block rather than a direct PLL clock that can be used internally. If you want access to LVDS_TX fast_clock PLL signal, you need to switch to ALTLVDS_TX external PLL option. Or generate 300 MHz clock with other PLL.
Regards
Frank
FvM
Super Contributor
11 months agoHi Rob,
you are right, no Cyclone 10 LP I6 speed grade available, unfortunately. Go for Agilex 3?
Best regards
Frank