jerry_anto
New Contributor
New ContributorLVDS receiver PLL
For the requirement of our project, we wanted to use 3 lvds receivers, each for one video in.
Unfortunately since each lvds receiver uses one pll, the pll usage increases. We are using one pll for mipi (MIPI PLL) and one for generating transceiver clock (PLL 50) .
The issue with using these 5 PLLs is one of my LVDS_RX and MIPI PLL are in the same bank (4A), the chip planner is trying to place both in the same location. ( X68 Y0) approx.
We tried several ways to use a single pll for all 3 lvds_rx but it didn't work.
1) use external PLL using the Mega-wizard.
2) Using alt clk ctrl IP
It would be really helpful if we get a solution to use one pll for all the lvds receivers.
